The present invention relates to a semiconductor device.
In recent years, portable electronic instruments have been increasingly reduced in weight and size, and research and development aiming at reducing the size of a semiconductor device provided in such electronic instruments have been conducted. As such a technology, a method has been proposed in which a low-voltage transistor for low-voltage operation and a high-voltage transistor for high-voltage operation are provided on a single substrate (single chip) to reduce the size of the entire semiconductor device provided in an electronic instrument (e.g. JP-A-2003-258120).
In this case, a parasitic MOS transistor may operate due to a high potential of a wiring layer electrically connected with the high-voltage transistor, whereby the semiconductor device may malfunction.